SIS M650 A1 VGA Chipset IC

Description:

SiSM650 IGUI Host Memory Controller integrates a high performance host interface for Intel® Pentium® 4 processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X interface, and SiS MuTIOL® Technology connecting w/ SiS961 MuTIOL® Media I/O.

SiSM650 Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated on-die termination to support Intel® Pentium® 4 series processors with FSB 100MHz and over clocking up to 133MHz. SiSM650 provides a 12-level In-Order-Queue to support maximum outstanding transactions up to 12. It integrated a high performance 2D/3D Graphic Engine, Video Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for the Intel Pentium 4 series based PC systems. It also integrates a high performance 2.7GB/s DDR333 Memory controller to sustain the bandwidth demand from the integrated GUI or external AGP master, host processor, as well as the multi I/O masters. In addition to integrated GUI, SiS M650 also can support external AGP slot with AGP 1X/2X/4X capability and Fast Write Transactions. A high bandwidth and mature SiS MuTIOL® technology is incorporated to connect SiSM650 and SiS961 MuTIOL® Media I/O together. SiS MuTIOL® technology is developed into three layers, the Multi-threaded I/O Link Layer delivering 1.2GB bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multi-threaded I/O Link layer, the Multi-threaded I/O Link Encoder/Decoder in SiS961 to transfer data w/ 533MB/s bandwidth from/to Multi-threaded I/O Link layer to/from SiSM650, and the Multi-threaded I/O Link Encoder/Decoder in SiSM650 to transfer data w/ 533MB/s from/to Multi-threaded I/O Link layer to/from SiS961.

The memory controller can support both DDR and SDR. It can offer bandwidth up to 2.7GB/s under DDR333, 2GB/s under DDR266 and 1GB/s under PC 133 in order to sustain the bandwidth demand from host processor, as well as the multi I/O masters and AGP masters. Delivering a high performance data transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or external AGP master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by retaining the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The SiSM650 adopts the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by organizing the frame buffer in the system memory.

The Integrated GUI features a high performance 3D accelerator with 2 Pixel / 4 Texture, and a 128 bit 2D accelerator with 1T pipeline BITBLT engine. It also features a Video Accelerator and advanced hardware acceleration logic to deliver high quality DVD playback. A Dual 12- bit DDR digital video link interfaced to the Video Bridge is incorporated to expand the SiS M650 functionality to support the LCD or TV display. The CRT display and the LCD or TV display can be supported by the Dual View Capability, in the other words that both can generate the display in independent resolutions, color depths, and frame rates. Two separate buses, Host-t-GUI in the width of 64 bit, and GUI-t-Memory Controller in the width of 128-bit are devised to ensure concurrency of Host-t-GUI streaming, and GUI-t-MC streaming. In PC133, DDR266 or DDR333 memory subsystem, the 128 bit GUI-t-MC bus will attain the AGP4X, AGP 8X equivalent or higher texture transfer rate, respectively. The Memory Controller mainly comprises the Memory Arbiter, the M-data/M-Command Queues, and the Memory Interface. The Memory Arbiter arbitrates a plenty of memory access requests from the GUI or AGP controller, Host Controller, and I/O bus masters based on a default optimized priority list with the capability of dynamically prioritizing the I/O bus master requests in a bid to offering privileged service to 1) the isochronous downstream transfer to guarantee the min. latency & timely delivery, or 2) the PCI master upstream transfer to curb the latency within the maximum tolerant period of 10us. Prior to the memory access requests pushed into the M-data queue, any command compliant to the paging mechanism is generated and pushed into the M-CMD queue. The M-data/M-CMD Queues further orders and forwards these queuing requests to the Memory Interface in an effort to utilizing the memory bandwidth to its utmost by scheduling the command requests in the background when the data requests streamlines in the foreground.

Features:

• Part Number : SIS M650 A1
• Package : BGA
• Manufacturer : SIS

Package included:

• 1 x SIS M650 A1 VGA Chipset IC